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Magazine Name : Ieee Journal Of Solid-State Circuits

Year : 2005 Volume number : 40 Issue: 05

A 12-Bit 80-Msample/S Pipelined Adc With Bootstrapped Digital Calibration (Article)
Subject: Adaptive Systems , Analog-To-Analog Conversion , Bootstrapped Calibration , Cmos Analog Integrated Circuits
Author: Carl R. Grace      Paul J Hurst     
page:      1038 - 1046
A 15-B 40-Ms/S Cmos Pipelined Analog-To-Digital Converter With Digital Background Calibration (Article)
Subject: Analog-Digital Conversion , Calibration , Mixed Analog-Digital Integrated Circuits
Author: Hung-Chih Liu      Zwei-Mei Lee     
page:      1047 - 1056
A 150-Ms/S 8-B 71-Mw Cmos Time-Interleaved Adc (Article)
Subject: Analog-Digital (A/D) Conversion , Cmos Analog Integrated Circuits , Comparators , Folding A/D Converters
Author: Sotirios Limotyrakis      Scott D. Kulchycki     
page:      1057 - 1067
Low-Voltage Super Class Ab Cmos Ota Cells With Very High Slew Rate And Power Efficiency (Article)
Subject: Adaptive Biasing , Analog Cmos Circuits , Class Ab Amplifiers , Low-Voltage Cmos Circuits
Author: A. J. Lopez-Martin      Sushmita Baswa     
page:      1068 - 1077
A Cmos Transconductor With Multidecade Tuning Using Balanced Current Scaling In Moderate Inversion (Article)
Subject: Analog Cmos Circuits , Continuous-Time Filters , Low-Voltage Cmos Circuits , Moderate Inversion
Author: Antonio J. Lopez-Martin      J Ramirez-Angulo     
page:      1078 - 1083
A Cmos Passive Mixer With Low Flicker Noise For Low-Power Direct-Conversion Receiver (Article)
Subject: Complementary Switches , Conversion Gain , Dc Offset Cancellation , Direct Conversion Receiver
Author: Sining Zhou      Mau-Chung Frank Chang     
page:      1084 - 1093
A 0.25-Um Cmos Quad-Band Gsm Rf Transceiver Using An Efficient Lo Frequency Plan (Article)
Subject: Cmos , Dc Offset , Direct Conversion , Frequency Divider
Author: Eunseok Song      Yido Koo     
page:      1094 - 1106
A Study Of Phase Noise In Colpitts And Lc-Tank Cmos Oscillators (Article)
Subject: Cmos , Colpitts , Lc-Tank , Oscillators
Author: Pietro Andreani      Xiaoyan Wang     
page:      1107 - 1118
A Vcdl-Based 60-760-Mhz Dual-Loop Dll With Infinite Phase-Shift Capability And Adaptive-Bandwidth Scheme (Article)
Subject: Adaptive Bandwidth , Analog Voltage-Controlled Delay Line (Vcdl) , Clock Synchronization , Delay-Locked Loop (Dll)
Author: Seung-Jun Bae      Hyung-Joon Chi     
page:      1119 - 1129
A Single-Path Pulsewidth Control Loop With A Built-In Delay-Locked Loop (Article)
Subject: Delay-Locked Loop (Dll) , Duty Cycle , Pulse Width Control Loop (Pwcl)
Author: Sung-Rung Han      Shen-Iuan Liu     
page:      1130 - 1135
Switching Noise And Shoot-Through Current Reduction Techniques For Switched-Capacitor Voltage Doubler (Article)
Subject: Break-Before-Make Mechanism , Charge Pump , Dc-Dc Cinverter , Shoot-Through Current
Author: Hoi Lee      Philip K.T. Mok     
page:      1136 - 1146
A High-Sensitivity Cmos Image Sensor With Gain-Adaptive Column Amplifiers (Article)
Subject: Cmos Image Sensor , Column Amplifier , Gain-Adaptive Amplifier , Low Readout Noise
Author: Masaki Sakakibara      Shoji Kawahito     
page:      1147 - 1156
Design Techniques For Single-Low-Vdd Cmos Systems (Article)
Subject: Cell Library , Charge Pump , Flip-Flop , Low Power
Author: Jinn-Shyan Wang      Hung-Yu Li     
page:      1157 - 1165
Design Analysis And Circuit Enhancements For High-Speed Bipolar Flip-Flops (Article)
Subject: Current Mode Logic , High-Speed , Keep-Alive , Open Circuit Time Constant (Octc)
Author: Thomas E. Collins      Vikas Manan     
page:      1166 - 1174
A Divide-By-16.5 Circuit For 10-Gb Ethernet Transceiver In 0.13-Um Cmos (Article)
Subject: Current-Mode Logic (Cml) , Divide-By-16.5 , Double-Edge-Triggered Flip-Flop (Dtff) , Frequency Divider
Author: Yongsam Moon      Sang-Hyun Lee     
page:      1175 - 1179
A 1.25-Gb/S Burst-Mode Receiver For Gpon Applications (Article)
Subject: Bicmos Integrated Circuits , Communication Systems , Optical Receiver , Passive Optical Networks (Pons)
Author: Peter Ossieur      Dieter Verhulst     
page:      1180 - 1189
A Low-Power 2.5-Ghz 90-Nm Level 1 Cache And Memory Management Unit (Article)
Subject: Cache Mamories , Computer Architecture , High-Speed Integrated Circuits , Low Power
Author: Jonathan R. Haigh      Michael W. Wilkerson     
page:      1190 - 1199
A 400-Mhz Random-Cycle Dual-Port Interleaved Dram (D2ram) With Standard Cmos Process (Article)
Subject: Cmos-Compatible , Embedded Dram , Random Cycle , Trench
Author: Masanori Shirahama      Yasuhiro Agata     
page:      1200 - 1207